The present invention relates generally to phase-shifting circuits and more particularly to phase-shifting circuits capable of being incorporated in a large number in an integrated circuit (IC) package of a limited number of pins.
For the purpose of subjecting an analog signal to a great time delay without waveform distortion, a delay circuit of an organization wherein a required number of phase-shifting circuits of flat frequency response characteristic are connected in cascade connection is used in many cases. These phase-shifting circuits contain capacitors within their circuits.
When phase-shifting circuits of known type are to be formed as an IC, since the capacitors used in the circuits become externally connected, two IC package pins are necessary for external connection of the capacitor of the phase-shifting circuit of each stage. Consequently, in the forming as an IC of a delay circuit comprising a large number of stages of phase-shifting circuits in cascade connection in order to obtain a large delay time, a large number of IC package pins for external connection of the capacitors become necessary.
However, IC packages are standardized by each IC manufacturer, and the arrangements and numbers of pins provided on the IC packages are also substantially standardized. The dual in-line packages (DlPs) widely supplied at present are ordinarily of the 14-pin and 16-pin type, and DlPs of particularly large number of pins are those of 40 pins and 42 pins. Since the numbers of pins of these IC packages are standardized by the manufacturers, and the numbers of pins are predetermined in this manner, the above mentioned delay circuit must be so designed for circuit integration as an IC that the number of pins required for external connection of the capacitors will not exceed the number of pins of the IC package. For this reason, in the case where a delay circuit employing known phase-shifting circuits is to be circuit integrated as an IC, the number of connected stages of the phase-shifting circuits to be connected in cascade connection is subject to limitation, whereby it has been difficult to integrate into an IC a delay circuit comprising a large number of phase-shifting circuits in cascade connection.